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Hardware Options for the Future

Anyone see this?

https://www.pulp-platform.org/


3.. 2.. 1.. Lift-off: Presenting Ariane

This year ETH Zurich and University of Bologna are celebrating 5 years of collaboration on the PULP project, and we are proud to present the newest member of the PULP family. Ariane is a Linux-ready, application-class, 64-bit RISC-V core supporting (RV64-IMC) written completely in System Verilog, and is available to download from our GitHub page immediately.

Ariane is a 6-stage, single issue, in-order CPU which fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like (Linux, BSD, etc.) operating system. It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer, branch history table and a return address stack). The primary design goal was on reducing critical path length to about 20 gate delays.

Following the feedback we will get from our users, we will continue the development of Ariane on the public repositories, and we have many features that we are working on for this core such as:

    IPC improvements
    Double precision floating point unit
    Full support for Atomics

and many more to come. You can access Ariane directly from our GitHub page and do not forget to follow us on Twitter (@pulp_platform).

… and we are not done yet!

We still have a couple of exciting new releases in the upcoming weeks in the multi-core space: as promised we will eventually share all our PULP development.

Stay tuned!!!